1. Field of the Invention
This invention relates to forming a metal pattern on the surface of a substrate and to the products resulting therefrom. More particularly, this invention relates to processes for forming metal patterns on insulating substrates suitable for the manufacture of printed circuit boards by metal plating, e.g., by electroless metal plating, and for forming metallic interconnecting holes or cavities suitable for the manufacture of wire scribed boards.
2. Description of the Prior Art
It is well known to apply an electroless metal plating to an insulating substrate such as plastic, by depositing a noble metal, activator or catalyst suitable for rendering the substrate receptive for electroless metal plating, and then exposing the substrate to an electroless metal plating solution. Various techniques have been used to form a circuit pattern on a desired circuit-forming area, including through-holes, on an insulating substrate by electroless metal plating. Among the processes utilized for forming printed circuit boards in the prior art is a fully additive process. A fully additive process is a process for obtaining conductive patterns by selective deposition of conductive material on unclad base material wherein the entire thickness of electrically isolated conductors is built up by electroless metal deposition.
A fully additive plating process has been employed in the production of wire scribed circuit boards with through-holes including wire assemblies such as those disclosed in U.S. Pat. Nos. 3,646,572; 3,674,914 and 4,097,864, all to Burr, the dislosures of which are hereby incorporated by reference.
Such wire scribed circuit boards are manufactured under the tradename Multiwire .RTM. and may include, for example, networks of fine insulated wires affixed to a surface of a substrate comprising a precatalyzed, epoxy glass laminate. Interconnection between these wires and other conductors are established by drilling perpendicular to the wire planes a hole of such a diameter and location that it intersects the wire, metallizing the barrel of the hole and the intersected tip of the wire, and soldering components or other connectors to the metallized hole.
The laminate substrate and the wiring adhesive layer both contain a catalyst for electroless deposition. A plating mask is applied before forming the holes (or cavities) to be metallized. The substrate then is immersed in an electroless metal bath to deposit metal on the exposed areas. Finally, the mask is stripped, and the substrate is subjected to post-treating operations. Because the catalytic material comprises only part of the laminate substrate and adhesive layer, e.g., part of a reinforced epoxy-glass substrate, its inherent catalytic effect is weak. Also, the electrolessly deposited metal coating tends to slowly cover glass fibers and at times may contain voids where bundles of glass fibers exist at the hole wall surface in the substrate. Voids are openings in a metal layer on a surface of a substrate or on the walls of a hole extending into or through the substrate, the openings being formed due to lack of metallization on the surface or on the hole walls.
An additional difficult plating problem is plating "blind vias" which are cavities having a diameter in the range of 160-600 microns extending from the surface and only partly through the substrate. Differentials in plating thicknesses in a blind via may occur which result in inadequate metal plating at the bottom of the blind via. Methods for producing blind vias in wire scribed boards are described in U.S. application Ser. No. 254,132, filed Apr. 14, 1981 to Lassen, the disclosure of which is incorporated herein by reference.
The production of a high-quality product has been difficult and required careful quality control primarily due to the fact that the precatalyzed laminate has low catalytic activity. To compensate for low catalytic activity on hole walls in the laminate, high activity plating baths have been used Plating baths with high activity are difficult to control. Moreover, a very active bath has a tendency to be unstable. If the bath is too active, extraneous metal deposits, i.e., copper dust particles, precipitate in the solution and drop to the bottom of the bath tank. The copper dust particles also will deposit on the product. These dust particles are incorporated into the metal deposit interrupting the grain structure of the deposit and forming nucleation sites for cracks. Cracks are breaks or fissures in a metal layer on a surface of a substrate or on the walls of a hole extending into or through the substrate as observable with 100X magnification. The breaks or fissures may be formed during metallization of the surface, or of the hole walls, or during soldering or other operations.
A high activity plating bath requires close supervision by the operator. Usually, such a bath is used for one plating cycle and then must be discarded, and disposed of as waste.
If the bath has not been sufficiently active, the copper layer deposited on the hole walls may contain voids and cracks.
Voids in the copper layer forming the "wrap-around area" are an additional quality control problem of additively plated wire scribed boards where the wire is severed when the hole is formed. A "wrap-around area" forms when insulation surrounding the wire (e.g., a polyimide jacket) is etched back during a hole cleaning operation. The insulation is etched back typically from about 0.005 mm to about 0.5 mm from the intersection of the wire with the hole wall. Then, this "wrap-around area" must be completely filled with a copper deposit which wraps around the wire where the wire intersects the hole wall. It is essential that a void-free and crack-free layer of copper be deposited in this region to produce a reliable product.
In one process for making a wire scribed board, an alkaline permanganate treatment has been used not only to remove resin smear(s) produced by a hole drilling step, but also to etch back the polyimide wire insulation to some extent. Following the permanganate treatment, the hole is "neutralized" and rinsed. Neutralizers such as SnCl12, formaldehyde or hydrazine-hydrate solutions have been used. However, despite the neutralization step, the permanganate treatment has been found to reduce catalytic activity of the precatalyzed base material. As a result, it has been necessary to operate the electroless copper plating bath in two different modes.
In an initial mode, because the catalytic activity is so low, the copper plating bath activity must be sufficiently high to form an initial copper film layer. After formation of such initial layer, the bath formulation is changed to a less active and more stable condition to complete the copper deposition. However, the time to form the initial copper layer is long. It takes 20 minutes to about 3 hours to electrolessly deposit an initial copper film onto a pattern on the substrate and within the though-holes. Switching between the two modes is sometimes difficult to control. As a result, the copper plating bath cannot be used on a continuous basis.
Additive plating processes also have been employed for producing printed circuits on non-catalytic substrates. In one process, a mask pattern is laid down on the surface of an insulating substrate. The entire surface, including both the mask and the exposed substrate areas, is treated and coated with a sensitizer and an activator, and then the entire surface is treated with a metal deposition solution. Metal deposits both on the exposed substrate areas and on the mask-covered areas. The mask and the metal coating electrolessly deposited on the mask are later removed by means of a solvent to leave only the desired metal conductor pattern. In this process, because of the relatively heavy formation of metal over the mask area, the edges of the conductors have a tendency to be ragged and hence resolution is not as good as required for precision uses.
Another electroless deposition process involves first sensitizing and activating the entire surface of an insulating substrate before applying a mask pattern. After the mask pattern is applied, the entire surface is treated with an electroless metal deposition solution. In this method, metal deposits predominantly on the sensitized and activated exposed substrate areas and not to any significant degree on the mask-covered areas. Resolution is good in this method, but the method has serious disadvantages, e.g., (1) in that sensitization and activation of the entire surface of the substrate produces a surface which may have a relatively low resistivity between conductors deposited thereon, and if spacing is to be very close, as is required in many of today's applications, this may cause electrical breakdown, and (2) manufacturing handling problems, in that during the long processing sequence between activating and finally electrolessly plating, the catalytic surface is highly sensitive to contamination, scratching, and the like which can result in defective circuits.
Another additive plating process for a non-catalytic substrate is described in U.S. Pat. No. 4,388,351 to Sawyer. According to such process, a printed circuit board is formed by applying a removeable negative mask pattern onto the surface of a non-catalytic substrate whereby portions of the surface are exposed in a positive pattern, forming micropores in the positive pattern portions of the substrate surface, sensitizing the positive pattern portion of the substrate and the negative mask to form thereon a catalytic species capable of catalyzing electroless metal deposition, optionally electrolessly depositing a thin porous flash metal deposit having a thickness of from 0.075 to 0.5 microns onto the delineated catalytic species in the circuit pattern, removing the negative mask and thereby the catalytic species and the flash electroless metal deposited thereon, and electrolessly depositing a metal onto the catalyzed positive pattern.
However, the process described in U.S. Pat. No. 4,388,351 has the deficiency of poor control of the edge definition of the conductor due to the mask stripping operation. The conductor edges are not adhesion promoted. When a thick copper buildup, e.g., about 35 microns, is required, copper adherently deposits on the center core of the conductor which has been adhesion promoted, which may have a width as small as 125 microns and grows out and up about the same, i.e., about 35 microns on each side of the conductor. Thus, 70 microns of a conductor width of 195 microns would not be bonded, rendering this process suitable only for coarse conductor patterns.
Still another additive plating process for a non-catalytic substrate is described in U.S. Pat. No. 3,799,816 to Schneble et al. According to this process, plated through-hole printed circuit boards containing thereon a printed circuit pattern are prepared by: forming holes in an insulating substrate at preselected points, applying a hydrophobic insulating mask on the circuit pattern, leaving the holes exposed, the mask being essentially activator-repellent, contacting the substrate with an activator solution comprising stannous ions and precious metal ions in solution to render the hole walls, but not the exposed surface of the hydrophobic mask, sensitive to the reception of electroless metal, contacting the substrate with an electroless metal deposition solution to deposit electroless metal on the exposed areas of the substrate including the hole walls, but not on the exposed surface of the hydrophobic mask, and treating the substrate with an etching solution a number of times to remove minor deposits of metal on the mask while leaving the electroless metal deposit on the exposed areas substantially unimpared, the etching solution being capable of dissolving the electroless metal (See column 3, lines 35-54 of U.S. Pat. No. 3,799,816).
U.S. Pat. No. 3,443,988 proposes a process for preventing deposition of electroless metal on masks by applying materials capable of neutralizing surface imperfections present on masking resins. However, since printed circuits require a long plating time, deposition of metal on masks is not prevented by such process.
U.S. Pat. Nos. 4,293,592 and 4,151,313 describe processes of preventing deposition of electroless metal on masks by utilizing hydrophobic masks containing pigments or additives to inhibit metal deposition in combination with organic acid washing solutions to wash the activation from the mask.
The masks comprise silk screen printed, epoxy resin based resists. Incorporated in the resists are inhibitors which inhibit the deposition of the noble metal catalyst on the mask so that smaller quantities of noble metal are deposited on the mask than on the circuit pattern. According to U.S. Pat. No. 4,151,313, the masking material must contain a solid solution of oxides of titanium, nickel and antimony. In addition, the noble metal which does deposit on the mask must be removed with a solution of hydrochloric acid and ammonium persulfate. According to U.S. Pat. No. 4,293,592, the masking material must contain 2-20 parts by weight of inhibitors such as sulfur, selenium, arsenic, zinc, antimony aluminum, iron, manganese, chromium, lead phosphorus, cadmium, vanadium, or oxides, chlorides, salts thereof. The noble metal which does deposit on the mask is removed with an aqueous solution of an organic acid and hydrochloric acid and/or nitric acid. The insulating substrate then is dipped in an electroless metal plating solution to form an electroless metal plating on a positive pattern of circuit. These processes teach away from applicant's invention because even though they disclose the use of inter alia, an alkaline accelerator solution, there is no suggestion of keeping the accelerator solution in contact with the substrate for a sufficient amount of time to remove essentially all catalyst species from the surface of the masks and by doing this avoid all other complicated steps.
Accelerator solutions have been used in electroless plating processes for many years. Their basic function is to complete the reaction between stannous chloride and palladium chloride from the activator and dissolve the resulting stannic tin. This results in active noble metal (palladium metal) sites on the circuit board substrate. At one time, some accelerator solutions comprised alkaline solutions containing complexing agents to dissolve the tin. However, acidic accelerators containing acids such as hydrogen fluoride, dilute fluoroboric acid, ammonium bifluoric acid, perfluoric acid and oxalic acid, have been preferred. These acidic accelerator solutions leave the activator in place, including the activator contamination on the mask.